1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device equipped with a plurality of ports.
2. Description of the Related Art
Multi-port memories, which are semiconductor memory devices equipped with a plurality of ports, can be classified into various types. When the term “multi-port memory” is used hereinafter, it refers to a memory that is provided with a plurality of ports, and that allows access to be independently made from any one of the ports to a common memory array. Such a memory may have an A port and a B port, and allows a read/write operation to be conducted with respect to the common memory array independently from a CPU linked to the A port and from a CPU linked to the B port.
A multi-port memory is equipped with an arbitration circuit called an arbiter. The arbiter determines priority of access requests received from the plurality of ports, and a control circuit of a memory array attends to access operations one after another according to the determined priority. For example, the earlier the arrival of an access request to a port, the higher priority the access is given.
In such a case, since the memory array is accessed from the plurality of ports at random, it is necessary to reset the memory array immediately after a read or write access operation is carried out, thereby making sure to be prepared for next access. That is, if a word line is kept in the selected state in response to an access from a given port, and column addresses are successively shifted to read successive data as in a column access operation generally used in DRAMs, access from another port will be kept waiting during this operation. Accordingly, it is necessary to reset the memory array immediately after each read or write operation.
Conventionally, an SRAM has typically been used as a memory array of a multi-port memory. This is because an SRAM allows high-speed random accessing, and, also, nondestructive read operation is possible.
In a multi-port memory having two ports, for example, one SRAM memory cell is provided with two sets of word lines and bit line pairs. One of the ports performs a read/write operation by using one set of a word line and a bit line pair, and the other one of the ports performs a read/write operation by using the other set of a word line and a bit line pair. In this manner, read/write operations can be independently carried out from the two different ports. However, since it is impossible to perform two write operations simultaneously when the two ports attempt to write data in the same cell at the same time, one of the ports is given priority to perform the write operation, and the other one of the ports is given a BUSY signal. This is called a BUSY state.
As a system develops to have improved performance, the amount of data treated by the system also increases. As a result, a multi-port memory needs a large capacity. The SRAM-type multi-port memories, however, have a drawback in that the size of a memory cell is large.
In order to obviate this, it is conceivable to adopt a DRAM array in a multi-port memory. In order to attain a significantly higher circuit density than multi-port SRAMs, one DRAM memory cell used for a multi-port memory needs to be connected to only one word line and one bit line in the same manner as a typical DRAM cell. If memory blocks are implemented by using DRAM cells in such a manner, one of the ports cannot access a given block if another one of the ports is carrying out a read or write operation with respect to this block. This is because only a destructive read operation is possible in a DRAM cell. That is, when information is read, another word line in the same block cannot be selected until this information is amplified and restored in the cell and a word line and a bit line are precharged.
For this reason, if a given port accesses a memory block that is being accessed by another port, a BUSY state will be detected. A BUSY state occurs in an SRAM-type multi-port memory only when a plurality of ports simultaneously issues write requests to the same memory cell. On the other hand, a BUSY state occurs in a DRAM-type multi-port memory when a plurality of ports simultaneously issues any types of access requests to the same memory cell. Therefore, the probability of BUSY occurrence in the DRAM-type memory is significantly greater than the probability of BUSY occurrence of the SRAM-type memory. Further, once in a BUSY state, the DRAM-type multi-port memory suffers problems that desired operations cannot be performed, or that processing becomes slow due to a waiting time.
Moreover, unlike an SRAM-type multi-port memory, a DRAM-type multi-port memory needs a refresh operation to be periodically performed for the purpose of maintaining stored information, so that some measure has to be taken to insure proper refresh timing.
Accordingly, the present invention is aimed at providing a DRAM-type multi-port memory that obviates problems particularly associated with DRAMs.